Søren SøeSoftware Development Manager, Xilinx Inc
M.Sc. Electrical Engineering, Technical University of Denmark
Ph.D. Computer Engineering, University of California
2100 Logic Dr
San Jose, California 95124, USA
Research InterestsLogic synthesis, Technology mapping, VLSI CAD, Formal methods in VLSI design.
Although I am interested in all aspects of VLSI design and CAD for VLSI, logic synthesis and in particular logic minimization has so far consumed most of my time.
At Xilinx Inc. I designed and implemented the core of the fitter that targets Xilinx's CPLD families. On top of the core, I designed and implemented applications for logic minimization, timing optimization, density optimization, and technology mapping. Several other developers used the core to implement other applications. As of today, the CPLD fitter consists of 250.000 lines of mostly C++ code.
My time as a graduate student was devoted to the UC Santa Cruz's If-Then-Else Minimizer ITEM, where Boolean functions are represented as if-then-else directed acyclic graphs. There my researched focused on technology independent transformations, with special emphasis on finding good variable orders that result in small canonical if-then-else DAGs. ITEM is implemented in C++.