I'm a first year PhD student in Computer Engineering at UCSC.
My research interests are in Computer Architecture, especially in Processor and Memory.
My current project is Processing-In-Memory (PIM).
Wrote the test plan according to the design;
Built up the UVM based testbench and the simulation environment;
Co-worked with design, algorithm and DSP firmware teams to accomplish the baseband data chain verification;
Designed, synthesized, mapped, placed and routed the QPI physical layer using Xilinx ISE;
Implemented main functions including lane deskew, linkwidth configuration and data scramble/descramble;
Verified the functions by running tests on the board which connects two CPUs using two QPI Physical layers;
The cache is used in the node controller which implements the Directory-based Cache Coherence Protocols;
Designed the main parts of the cache;
Proposed the scheme of a non-blocking cache which has the ability to work on other requests while waiting for memory to supply misses;
Implemented special handling of misses with same tags for reducing miss penalties;
Applied LRU policy for replacement;
Designed a hierarchical testbench using SystemVerilog;
Verified the cache based on constrained-random tests;
Coming on the way....
email: yzhu29@ucsc.edu