Peter Johnson

Software design using C, C++, and Perl.
Digital logic design using Verilog and Synopsys Design Compiler and Behavioral Compiler.
Excellent knowledge of IC testing including scan and BIST techniques.
Detailed knowledge of consumer graphics system design.
Knowledgeable with all phases of ASIC design.
Intimate knowledge of design tools and flows.
Able to manage and direct engineering projects.
Proven track record dealing with customers.
Silicon Engineering, Inc. 8/89 - present
Senior Member Technical Staff / Software Segment Lead
Digital logic design.
Software design of CAD tools.
Defining and implementing Silicon Engineering's design methods.
Training and managing junior engineers.
Maintaining and growing Silicon Engineering's software business.
Logic design
At speed test engine for 1GHz floating point vector processor
High performance 3D resterizer engine
92MHz 96bit Video Shifter
100MHz 32bit Video Shifter
Digital controller for a consumer toy.
Third generation frame-rate control algorithm for grey-scale LCDs.
Software design
HSpice compatable circuit analysis tools (Caliper)
Self-Test synthesis and scan stitching tool.
High performance cycle based logic simulator.
Synopsys synthesis library generator.
Assembler and relocating linker for a proprietary 8 bit microcontroller.
Compass Viewlogic design kit delay calculator.
LSI Viewlogic design kit delay calculator and rule checker.
Defined Silicon Engineerings current top-down system model approach to IC design.
Pioneered the use of high level design tools such as Synopsys Design Compiler.
Intel Corporation 6/87 - 8/89
Design Engineer
Digital logic design.
CAD software design.
IC design and development methods.
Logic design
Tape-out and verification of first generation VGA gate array.
Design of an LCD controller in a second generation VGA product.
Software design
CAD tools for reverse engineering gate arrays.
High performance netlist comparison program.
Helped define archive strategy for 486 microprocessor.
Worked toward standardized methods to manage future processor design environments.
Built-in self-test flip-flop with asynchronous input
US Patent 5,416,784
Built-in self-test tri-state architecture
US Patent 5,513,190
Built-in self-test global clock drive architecture
US Patent 5,533,032
On the Effectiveness of Simultaneous Self-Test Techniques
1992 IEEE VLSI Test Symposium
Automatic Synthesis of Self-Test using ASyST
University of California at Santa Cruz
Computer Research Laboratory Technical Report 91-39, 1991.
Master of Science in Computer Engineering
University of California, Santa Cruz, December, 1991
Bachelor of Arts in Computer Science and Mathematics
University of California, Santa Cruz, June 1987