Joel F. Darnauer
255 Mountain View Ave
Mountain View, CA 94041
Cell 650 224 6439
joel@alumni.cse.ucsc.edu
September 13, 2002


PROFESSIONAL EXPERIENCE

Juniper Networks, Sunnyvale, CA.
Board Design/Signal Integrity Engineer. June, 1999-present.

  • Qualified optical link based on parallel 2.5Gbps VCSELs. Selection and management of VCSEL and serdes vendors. Specification and characteriation of link power and jitter budgets, evaluation of line coding techniques, creation of board and system level diagnostics and component qualification plan.
  • Designed test boards to qualify GHz source synchronous links used in the T640 and T320 router platforms. Required knowledge of high speed board design, signal integrity, and FPGA design.
  • Board designer for several switch fabric cards for the T640 family of routers. Responsible for specifications, schematic capture using Viewlogic, Xilinx FPGA design, lab bringup and diagnostics.
  • Working knowledge of PCB layout and design, circuit simulation (hspice), CMOS circuits, high-speed IO timing, lossy transmission lines, high speed clocking, crosstalk, PLLs, bypass capacitors, and simultaneous switching noise.
  • Tool experience includes hspice, Viewlogic, CCT, Allegro, Timing designer. Several IC layout and DRC packages. Synplify and some FPGA design packages.
  • Significant lab and troubleshooting experience with network and spectrum analyzers, TDR/TDT, BERTs, and high speed digital oscilloscopes.
  • Silicon Graphics , Mountain View CA. August, 1996- May, 1999.
    Member of Technical Staff

  • Signal integrity support for GSN, a copper-based 500Mbps parallel interface using HIPPI-6400. Developed PCB stackups, ASIC high-speed link and SRAM timing, board routing rules. Managed cable vendors. Championed high-frequency design issues internally across ASIC design, diagnostics, EMC, manufacturing and layout groups.
  • Characterized microprocessor HSTL IO circuits and flip-chip packaging for IO buffer transient response, simultaneous switching noise, core noise.
  • Developed CAD tools and design flows to manage signal integrity rules from schematic capture through PCB layout for Viewlogic and Allegro.
  • Micromodule Systems, Cupertino CA. July, 1995-January, 1996.
    Student Intern
  • Developed specialized autorouter software for single-layer packages and test membranes. Required knowledge of computational complexity and topological routing algorithms. Used C, Lisp, Perl and DRACULA.
  • Computer Engineering, UC Santa Cruz. 1992-1996.
    Graduate Student Researcher.
  • Developed two generations of field programmable multi-chip modules (FPMCM) for reconfigurable computing applications. Coordinated the efforts of several graduate students for multi-year DARPA contracts. Responsible for feasibility studies, project planning, architectural specifications, electrical performance analysis, thermal design, physical design and verification, testing of silicon substrates and packages, and partitioning software.
  • Used SPICE to evaluate a plastic BGA package for a 1000-pin flip-chip IC. Modeled interconnect delays, simultaneous switching noise, and developed test structures to estimate yield of interconnect and flip-chip assembly processes. Developed innovative routing algorithms for pin and ball-grid array (PGA/BGA) packages using gridless autorouters.
  • National Science Foundation Summer Institute in Japan at MITI's Electrotechnical Laboratory. Summer, 1994.
    Visiting researcher.
  • Implemented circuit partitioning heuristics in prolog and common lisp.

  • AT&T Bell Laboratories, Murray Hill, NJ. Summer, 1992.
    Electronics Packaging Research Department, Visiting Researcher.

  • Deployed automated multi-chip-module routing software.

  • Delco Electronics, Goleta, CA. Summer, 1991.
    Engineering consultant.

  • Implemented an automatic datapath placement CAD tool in C.

  • EDUCATION

    Computer Engineering, University of California at Santa Cruz.

  • Regents Fellow.
  • M.S. December, 1993.
  • Ph.D. in March, 1997 for the dissertation Cost-Effective Architectures for Field Programmable Multi-Chip Modules.

  • Electrical and Computer Engineering, University of California Santa Barbara.

  • Bachelor of Sciences with Honors.  June 1991. GPA 3.51.
  • One-year exchange at International Christian University in Tokyo, Japan.

  • PUBLICATIONS

    Journal Articles
     

  • "A Silicon-On-Silicon Field Programmable Multichip Module (FPMCM)---Integrating FPGA and MCM Technologies". Joel Darnauer, Porfirio Garay, Tsuyoshi Isshiki, John Ramirez, Wayne Wei-Ming Dai. IEEE Transactions on Components, Packaging, and Manufacturing Technology Part B. November 1995, Volume 18, Issue 4.
  • "Electrical evaluation of flip-chip package alternatives for next-generation microprocessors". Joel Darnauer, Dave Chengson, Bill Schmidt, Ed Priest, Dave Hanson, and Bill Petefish.  IEEE Transactions on Advanced Packaging, August 1999.

  • Conference Papers

  • "Electrical evaluation of flip-chip package alternatives for next-generation microprocessors". Joel Darnauer, Dave Chengson, Bill Schmidt, Ed Priest, Dave Hanson, and Bill Petefish. 1998 Electronic Components and Packaging Technology Conference.
  • "Tradeoffs in Chip and Substrate Complexity and Cost for Field Programmable Multichip Modules -Part II: The Clique Architecture". Joel Darnauer and Wayne Wei-ming Dai. ASME Interpack. June, 1997.
  • "Tradeoffs in Chip and Substrate Complexity and Cost for Field Programmable Multichip Modules". Joel Darnauer and WayneWei-ming Dai. First Workshop on Innovative Systems In Silicon. October, 1996
  • "A Method for Generating Random Circuits and its Application to Routability Measurement". Joel Darnauer and Wayne Wei-ming Dai. 1996 ACM Symposium on Field Programmable Gate Arrays.
  • "Field Programmable Multi-chip Module: an Integration of FPGA and MCM technology". Joel Darnauer, Porfirio Garay, Tsuyoshi Isshiki, John Ramirez, Wayne Wei-Ming Dai. 1995 Multi-Chip Module Conference.
  • "Design of FPGAs with Area I/O for Field Programmable Multi-chip Module". Vijayshri Maheshwari, Joel Darnauer, John Ramirez, Wayne Wei-Ming Dai. 1995 Symposium on Field Programmable Gate Arrays.
  • "A First-Generation Field Programmable Multichip Module". Joel Darnauer, Porfirio Garay, Tsuyoshi Isshiki, John Ramirez, Wayne Wei-Ming Dai. 1994 IEEE Workshop on FPGAs for Custom Computing Machines.
  • "Fast Pad Redistribution from Periphery-IO to Area-IO". Joel Darnauer and Wayne Wei-Ming Dai. 1994 IEEE Multi-Chip Module Conference.
  • "A 1024-Pin Plastic Ball Grid Array for Flip Chip Die". Andy Switky, Vijay Sajja, Joel Darnauer, Wayne Wei-Ming Dai. 1994 Electronic Components and Technology Conference.

  • Dissertation

  • Cost-Effective Architectures for Field-programmable Multi-chip Modules."  Joel Darnauer.  University of California at Santa Cruz, Computer Engineering Board of Studies, March 1997.

  • Technical Reports

  • "Planar Interchangeable 2-Terminal Routing". UCSC CRL Technical Report 95-49. October, 1995. Man-Fai Yu, Joel Darnauer, and Wayne Wei-Ming Dai.
  • "The Planar Pin-Assignment and Routing Problem is NP-complete". UCSC CRL Technical Report 95-41. August, 1995. Joel Darnauer.