Jeffrey Thomas Butera

Professional Experience

• Graduate Teaching Assistant – Present Sept. 2011– University of California, Santa Cruz - Computer Engineering
  Assist professor with instructional responsibilities, holding recitations/labs, and
  grading assignments and exams.
  
• CS Summer Research Assistant/Lab Technician – Aug 2010 May 2010– Haverford College, Haverford, PA
  Assist in Parallel Computing research using Apache Hadoop and OpenMPI.
  Maintain and upgrade the computer science research lab.
• Computer Science Lab Assistant/Grader – May 2011 Aug 2008– Haverford College, Haverford , PA
  Assist students with computer science lab work and programming.
  Grade student labs.

Education

• B.S. Computer Science with Honors – Haverford College, Haverford, PA May 2011 Aug 2007–
  • Related Courses: Introduction to Computer Science, Introduction to Data Structures, Principles of Computer Organization, Concurrency and Co-Design in Operating Systems, Analysis of Algorithms, Theory of Computation, CS Research Foundations, Multi-variable Calculus, Principles of Programming Languages, Software Development for Accessibility, Scientific Computing: Continuous Systems, Web Design and Development, Senior Thesis
  • Extracurricular Activities: Captain-Haverford College Baseball Team, Co-President and Co-Treasurer-Haverford Fishing Society, Member-Haverford Outdoors Club.
  • Languages Spoken: English, Spanish

Significant Projects

• Parental Advising Widget – Haverford College 2010
  Software project that allows parents to rank and regulate the websites that thier children can view. The program is equipped with a Firefox extension/toolbar that allows for real-time website ranking and blocking(Javascript, JSON, XML, CSS). There is also a Python, with CherryPy framework, backend to handle communication between the project website, the Firefox Extension, and the SQLite ratings database.
• Senior Thesis – Haverford College 2010
  Focused on Simultaneous Multithreaded processor architectures, specifically how SMT combines thread-level parallelism and instruction level-parallelism via dynamic thread scheduling. I also investigated the effect of increasing parallelism, or the number of instructions per cycle, on the overall performance of the processor and its power consumption in comparison to superscalar and multithreaded architectures.

Papers

• Rethinking Instruction-Set Design for Energy-Efficient Computing – 2011
  Co-Authors: Sol Lutze and David Wonnacott
  Submitted to Workshop on Energy-Efficient Designs (WEED) 2011, Denied

Honors and Awards

• Haverford College Baseball 2010–2011
  Third-Team All-Mid Atlantic Region 2010 & 2011, First-Team All-Centennial Conference 2010 & 2011, NCAA Division III National Co-Hitter of the Week by the National Collegiate Baseball Writers Association (NCBWA) (3/18/10)